Today, more and more products use cameras and sensors to capture large amounts of data. How do you aggregate and process it all? The Ti60F100, a second-generation 16nm FPGA from Elinis, can help you. The Ti60F100 features 60,000 logic cells, high-speed I/O configurable for various protocols, and built-in SPI Flash and Hyper-RAM, all in a tiny 5.5*5.5mm package with only 0.5mm pitch.

 

The Ti60F100 integrates logic and memory, making it an ideal solution for a wide range of camera and sensor systems. With SPI Flash, you don't need an additional configuration chip; the integrated Hyper RAM can store user data, for example: it can be used as a frame buffer for video processing applications.

 

The Ti60 High Speed I/O (HSIO) pins support a variety of single-ended and differential I/O standards. You can use them as regular GPIO or LVDS, or you can use them as MIPI Rx or Tx channels running at speeds up to 1.5Gbps. These HSIO pins are fully user-configurable, so you can mix and match them to meet your system requirements.

 

The compressed Ti60 bitstream file typically uses only about half of the SPI Flash space, and the rest can be used to store other data, such as software files for the RISC-V SoC core.

The HyperRAM memory in the F100 package has a capacity of 256Mbits and a clock rate of up to 200MHz, and features a HyperBus interface for high-speed communication. The memory supports double data rates of up to 400Mbps per channel and a 16-bit data bus with a bandwidth of up to 6.4G. The on-chip memory allows you to store video frame data or sensor data and then process it using FPGA logic cells, saving space on the board for memory placement.

 

Efifinity® Software's Interface Designer makes it easy to use HyperRAM by simply placing the HyperRAM module into your interface design and then connecting the pinout design to your RTL design. The software also includes a sample HyperRAM design for the Ti60F100, so you can easily get started.

FPGAs typically require a separate device to store configuration (bitstream) files. The F100 package has a 16Mbit SPI Flash, so you don't have to make room on the board for a configuration chip. The Ti60 is clocked at up to 85MHz to keep the chip in a wake-up state and ready to run fast.

 

In addition, the internal Flash can do more than just save bitstreams. The Efifinity software supports bitstream compression for Titanium FPGAs, and the compressed Ti60 bitstream file uses only about half of the Flash space. You can use the rest to store non-volatile user data, a second bitstream file, or even a RISC-V application. In addition, if security is a concern in your design, we can support the generation of bitstream files that are protected by authentication, encryption, or both.

 

The SPI pins of the Flash are tied to the F100 package pins. This design allows you to use the Ti60 FPGA as an SPI master device connected to additional slave devices (on-board Flash and SPI-enabled external devices). For example, you can use the SPI bus to collect data from SPI sensors for processing.